1. Field of the Invention
This invention relates to the field of semiconductor integrated circuit fabrication, and, in particular, to the field of fabricating transistors within semiconductor integrated memory cell circuits.
2. Background Art
Generally, a memory device can be a volatile memory device or a nonvolatile memory device. In volatile memory devices, old information can be erased and new information can be stored. In nonvolatile memory devices, programmed information is stored in the memory cells permanently.
The most common type of volatile memory device is the random access memory (RAM). RAMs are arrays of memory cells that store one bit of information in binary form. Information can be randomly written into or read out of each memory cell of RAMs as needed. Thus RAM is a read-write memory.
Read only memory (ROM) is a common type of nonvolatile memory device. Information is permanently stored in ROMs, as previously described, and thus only read operations can be performed.
Other types of nonvolatile memory devices, include erasable programmable memory (EPROM), electrically-erasable programmable memory (EEPROM) and flash EPROM memory. In EPROMs, EEPROMs and flash EPROM memories the stored information is erasable and new information can be programmed. These nonvolatile memories are programmed in substantially similar ways. However, the erasing operations of these memories are different. The EPROM can be erased only with ultraviolet light. The EEPROM and the flash memory can be erased electrically. EEPROMS and flash memories are therefore referred to as electrically alterable devices.
The EPROM and the EEPROM are basically the same in their fundamental structure and operation. However, the structure of the flash memory is different. For example, the flash memory cell is a single transistor memory cell, as compared with the more complicated architectures of the other erasable read only memory devices. Additionally, flash memories have floating gates.
Flash memories are finding widespread use in the smaller die sizes required in present day applications. One reason for their widespread use in smaller die sizes is the high memory cell densities that can be achieved using them. The major reason for the high density that is possible in flash memory cells is their single transistor architecture. Another reason they are finding widespread use is that they can be efficiently manufactured at low cost.
The transistors of floating gate flash memory cells are programmed by applying an electric field that injects hot electrons into the floating gates in order to store a charge oil the gates. The charge stored on the gates changes the effective threshold voltage of the transistors. This can be sensed by determining the voltage required to turn the transistor on.
The floating gates of the memory cells are deprogrammed by leaking the charge from the floating gates through an oxide layer into the substrate. The mechanism for leaking the charge from the gates is Fowler-Nordheim tunneling. One problem with floating gate flash memories is that the tunneling of electrons in this manner to deprogram the cells degrades the oxide through which the tunneling occurs.
In scaling erasable nonvolatile memory cells such as flash memory cells down to submicron dimensions however, problems arise. For example, the programming speed of the smaller devices is lower than the speed of the larger devices. Accordingly, the degree to which flash memory cells can be scaled down and integrated is restricted.
The problem of increasing the speed of flash memory cells is addressed in U.S. Pat. No. 5,432,106 entitled "Manufacture of Asymmetric Non-Volatile Memory Cell," issued on Jul. 11, 1995, to Hong. In particular, Hong teaches an asymmetric transistor for use in flash memory cells. In the transistor taught by Hong, source and drain ion implantation is provided using a large angle implant between about 15.degree. and 45.degree.. This angle generates an offset in the formation of the source and drain regions of the transistor. The offset in the transistor is provided in order to permit faster programming and deprogramming of the transistor.
U.S. Pat. No. 5,362,685, entitled "Method For Achieving A High Quality Thin Oxide in Integrated Circuit Devices," issued to Gardner et al. on Nov. 8, 1994, also addresses the problem of increasing the programming speed of flash memory devices. Gardner et al. teaches a gate oxide having varying thicknesses underneath the gate of a transistor. In the method taught by Gardner an etch operation is performed to provide a gate oxide over only a portion of a transistor channel region. An oxidation step then increases the thickness of the oxide gate while also growing oxide upon the surface area of the semiconductor.
It is therefore an object of the present invention to provide an improved flash memory cell within a semiconductor integrated circuit.
It is a further object of the present invention to provide an improved transistor structure within a flash memory cell.
It is a further object of the present invention to provide a flash memory cell that is less subject to degradation due to Fowler-Nordheim tunneling.
In particular, it is an object of the present invention to provide a transistor within a flash memory cell which permits faster programming and deprogramming of the flash memory cell.
These and other objects and advantages of the present invention will become more fully apparent from the description and claims which follow or may be learned by the practice of the invention.